The invention relates to a semiconductor device comprising a semiconductor body having at least a storage site with an insulated gate electrode, the semiconductor body having a surface contiguous to at least an electrode region which serves as electrode and forms a rectifying junction with a semiconductor region of a first conductivity type common to the electrode region and the storage site, the electrode region, viewed on the surface, being contiguous to an active semiconductor region which has a boundary which is defined for a given part by the adjoining electrode region and for at least a further part by a thick insulating layer serving as field insulation, a thin insulating layer being present on the active region. Said thin insulating layer comprising at least a first and a second sublayer, the second sublayer being separated by the first sublayer from the active region and a boundary layer being present at and/or near the interface between the first and the second sublayer, in which boundary layer charge can be stored which determines the information content of the storage site, while a gate electrode isolated from the active region extends over the sublayers, which gate electrode is extended at the further part of the boundary of the active region defined by the field insulation to above the field insulation.
Such a semiconductor device is known from "Proceedings of the I.E.E.E.", Vol. 64, No. 7, July 1976, p. 1039-1059. The storage site forms part of a memory field effect transistor, the active region being situated between a source and a drain electrode region. In this publication, one of the problems which may occur in such memory transistors is described as "Sidewalk Effect" on p. 1047. Between the thick field insulation and the thin insulating layer there is present a transition region in which the thickness of the insulating material increases gradually. Repeated writing and erasing in the memory transistor will result in that stored charge will gradually also accumulate in the boundary layer underneath the gate electrode in the transition region. Consequently, the threshold voltage in the transition region will vary. The value of this threshold voltage will lie between the high and the low threshold voltage of the memory transistor proper. Reading of the storage condition of the memory transistor may now give rise to problems due to the fact that in the condition with high threshold voltage, in which the memory transistor proper is not conducting when it is read out, passage of current under the transition region nevertheless becomes possible. This problems can be solved by providing under the transition regions in the semiconductor body more highly doped surface regions of a conductivity type opposite to that of the source and drain electrode regions of the memory transistor. The doping concentration in these surface regions is chosen so that the threshold voltage in situ is already sufficiently high to prevent a passage of current under the transition regions.
The solution described may give rise to difficulties in practice. As is known, writing and erasing in memory transistors of the kind described requires comparatively high voltages. These voltages may amount to 25 or 30 and sometimes 35 volts. Consequently, comparatively high requirements are imposed on the breakdown voltages of the rectifying junctions between the source and drain electrode regions and the common semiconductor region. The use of more highly doped surface regions under the transition regions may readily lead to comparatively low breakdown voltages if the distance between these surface regions and the source and drain electrode regions are not kept sufficiently large. The distance required leads to memory transistors having a comparatively large channel length which could be reduced only with a corresponding reduction of the breakdown voltage.